The present invention relates to a semiconductor memory device and, particularly, to a semiconductor memory device in which at least two physical addresses can be assigned to each memory cell thereof by providing for variable address decoding.
FIG. 1 shows schematically a construction of a conventional semiconductor memory device 1, in the form of a random access memory (RAM) having a common line serving as a data input as well as a data output line between a data input/output terminal 2 and a semiconductor memory. The semiconductor memory device 1 stores data and uses the data input/output terminal 2 for external data transfer. It also includes a read/write (R/W) terminal 3 for receiving an instruction signal to select an operation mode of the memory device, whether a read operation or a write operation. A chip select (CS) terminal 4 receives a chip selection signal to select one of the chips constituting the memory device 1. Address input terminals 5-1-5-n receive signals determining addresses of the memory cells to be accessed.
The address terminal 5-1 is for a 0-th address input bit and the address terminal 5-n is for a (n-1)th address input bit. The total number n of the address input terminals is usually determined such that a total number of internal memory cells of the memory device becomes 2.sup.n. That is, the number n of the address input terminals can be represented by n=log.sub.2 N where N is the total number of the internal memory cells.
FIG. 2 is a block diagram of an example of the semiconductor memory device shown in FIG. 1. In FIG. 2, the semiconductor memory device 1 includes a data read/write (R/W) control circuit 7, a data buffer circuit 8 and an address decoder circuit 10. A memory cell array 11 usually includes 2.sup.n memory cells and constitutes a memory circuit of the semiconductor memory device 1. Finally, there is a memory read/write control circuit 12.
The data R/W control circuit 7 receives signals from the R/W select terminal 3 and the chip select terminal 4 and supplies a R/W control signal 14 to both the memory R/W control circuit 12 and the address decoder circuit 10. The data R/W control circuit 7 also supplies a data buffer control signal 9 to the data buffer circuit 8 to thereby control the data R/W operation of the semiconductor device 1.
The data buffer circuit 8 is responsive to the data buffer control signal 9 for controlling a data transfer between the data input/output terminal 2 and the memory R/W control circuit 12.
The address decoder circuit 10 is responsive to R/W control signal 14 for decoding n address signals from the n address input terminals 5-1-5-n and selecting memory cells corresponding to these address signals.
The memory R/W control circuit 12 is responsive to the R/W signal 14 for controlling a data transfer with to or from the memory cells selected according to the address signals.
The data buffer circuit 8 and the memory R/W control circuit 12 are mutually connected through an internal data line 13. The memory R/W control circuit 12 is further supplied with a signal from the address decoder circuit 10 by a connection which is not shown.
The memory R/W control circuit 12 is usually composed of a sense amplifier and an internal data line buffer and the like. The signal for selecting one of the memory cells of the memory cell array 11 is provided by the address decoder circuit 10.
An operation of the semiconductor memory device 1 will be described with reference to FIG. 2 for a data write mode. First, the address of the memory cell in which data is to be written is supplied to the input terminals 5-1-5-n and the chip select terminal 4 is made active to select one or more memory cells. At the same time, data to be written in the memory cell is supplied to the data input/output terminal 2 and a write enable signal is supplied to the R/W terminal 3. The data R/W select control circuit 7 responds to the signals from the chip select terminal 4 and the R/W select terminal 3 to produce the data buffer control signal 9 which is supplied to the data buffer circuit 8. The data buffer circuit 8 responds to the data buffer control signal 9 to transfer the data supplied to the input/output terminal 2 to the internal data line 13. The address decoder circuit 10 decodes the address signals given from the address input terminals 5-1-5-n and selects one of the memory cells of the memory cell array 11 which corresponds to the address determined by the address signals. The memory R/W control circuit 12 responds to the R/W control signal 14 supplied from the data R/W control circuit 7 to write the data on the internal data line 13 into the memory cell selected by the signal (not shown) supplied from the address decoder circuit 10.
When a piece of data is to be read out from the semiconductor memory device 1, an address of a memory cell from which the data is to be read out is supplied to the address input terminals 5-1-5-n the chip select terminal 4 is set active and the R/W select terminal 3 is set to indicate a readout mode. The address decoder circuit 10 decodes the address signal given to the address input terminals 5-1-5-n, in the same manner as in the case of the writing operation, to select one of the memory cells of the memory cell array 11 that corresponds to the supplied address. The memory R/W control circuit 12 responds to the signal from the address decoder circuit 10 and the R/W control signal 14 from the data R/W control circuit 7 to read out a bit of information contained in the selected memory cell and to send it to the internal data line 13. The information sent to the internal data line 13 is transferred to the data input/output terminal 2 through the data buffer circuit 8 which operates in response to the data buffer control signal 9 from the R/W control circuit 7.
In the conventional semiconductor memory device as mentioned above, the determination of a particular memory cell of the memory cell array 11 is performed by the n address signal bits supplied externally to the n address terminals 5-1-5-n. Further, in the conventional memory device, a redundancy circuit is provided to avoid defective portions of the memory cells and the like and to use a memory cell which is physically different from that assigned by the address signal supplied to the address input terminals. Even in such a case, however, a memory cell selected according to a bit of addressing given through the address input terminals to the address line is definitely determined and thus it is impossible to access the same memory cell by sending a different address.